\section{Conclusion}
 
%We have presented a means to  an effective self-healing electromigration compensation mechanism. Our design is based on 130nm Globalfoundry process and 45nm NCSU FreePDK. The IR drop simulation is performed in Cadence EM/IR analysis tool. The result of applying our technique to various designs at different technology nodes was an observed 3-10 times increase in  MTTF. The EM effect of different techonology shows an deterioration trend. Our method is not limited to package plan and directly placed on the most severe EM part of the power network. Due to the straight forward optimization methodoloty and small performance overhead, our approach can be easily integrated with today's EDA flow. 

%We have presented a means to perform bidirectional current on power rails for on chip electromigration self-healing. This method introduced a new power network topology and is implemented into three designs under two different processes. The design is not limited to package plans and it can directly improve the most severe EM locations in a power network. We explored two approaches to further optimize the EM MTTF, which were the compensation strip locations changing and control duty ratio changing. The duty ratio changing method was more timing efficient and effective. Thus we gave an algorithm to integrate it into EDA flow. The result showed 3-10 times increase in the MTTF by applying our technique to various designs. The area overhead was around 4\%.


Electromigration (EM) is one of the major reliability issues for IC designs, and can cause wire wear-out with open-circuit failures or short-circuit failures for the interconnects in integrated circuits. The power supply network is the most EM-vulnerable component on a chip due to its large current density and uni-directional current flow. In this paper, we have proposed a novel solution based on the electromigration AC healing effect with compensation strip insertion. The proposed method uses simple control logics to apply balanced amount of current in both directions of power rails and therefore mitigate the EM effects. The post layout simulation on multiple designs with two technologies nodes (130nm and 45nm) shows 3X-10X increase of the mean time to failure (MTTF) with a small (3\%-5.5\%) area overhead.
